a. Field of the Invention
The present invention relates to an emitter coupled logic (ECL) circuit, and more particularly, to an emitter coupled logic circuit having an improved active pull-down circuit.
b. Description of the Related Art
Conventional ECL circuits are well known in the art. FIG. 1 is a schematic diagram illustrating a conventional ECL circuit. The conventional circuit consists of a current switch circuit having transistors Q1, Q2, Q3 and resistors R1, R2, R3 and an emitter follower circuit having transistor Q4 and pull-down resistor R4. Further, 1 and 2 denote input terminals, 3 denotes an output terminal, and 4 denotes a threshold voltage terminal. The conventional ECL circuit illustrated in FIG. 1 is a 2-input NOR gate. A constant current power source may be used in place of the resistor R3.
The operation of the conventional ECL circuit illustrated in FIG. 1 and the problems associated therewith are discussed below.
When collector voltages of transistors Q1 and Q2 change to a logical high level from a logical low level, transistor Q4 of the emitter follower circuit becomes conductive charging a capacitive load CL connected to the output terminal 3. In this case, because the emitter impedance of transistor Q4 is sufficiently low, the capacitive load CL is quickly charged up.
On the other hand, when one of the collector voltages of transistors Q1, Q2 of the current switch circuit changes to a low level from a high level, the capacitive load CL discharges through pull-down resistor R4 which is connected in series with the emitter of transistor Q4. In this case, when pull-down resistor R4 has a sufficiently small resistance value, the capacitive load CL can be quickly discharged. However, when pull-down resistor R4 is sufficiently small in resistance value, a large current flows continuously into the transistor Q4 which increases power dissipation. As a result, in the case of a large scale integrated circuit (LSI) with a high packing density, although a small resistance value is desired, to obtain a low power dissipation a pull-down resistance value which is too small cannot be selected. Thus, the discharge time of the capacitive load CL is slower than desired. This problem becomes more troublesome as the capacitive load CL increases.
This problem also results if a constant current source is used in place of pull-down resistor R4 to discharge the capacitive load CL. When a current level of the current source is high, the capacitive load CL can be quickly discharged. However, as the current level increases so does power dissipation. Accordingly, a high current level cannot be used because it would result in large power dissipation which is unsuitable for high density LSIs.
Therefore, when the capacitive load CL is large, a transient time for changing the output to a low level from a high level becomes longer than that for changing the output to a high level from a low level. As a result, the transient times for changing to a low level from a high level and for changing to a high level from a low level are unbalanced. These unbalanced transient times result in problems in design, namely timing, logical structures and actual operation.
An active pull-down type ECL circuit has previously been proposed to solve this dilemma. Such a circuit discharges the capacitive load CL into a low impedance when the output changes to a low level from a high level in place of the pull-down resistor R4 or constant current source. FIG. 2 is a schematic diagram of an active pull-down type ECL circuit associated with the prior art. The circuit consists of transistors Q11-Q17, resistors R11-R15, and capacitors C11, C12. A DC bias voltage is applied to the base of pull-down transistor Q17 to operate it as a constant current source with a circuit consisting of transistors Q14, Q15 and resistor R14 so that a low current flows continuously. This structure is used because transistors which are in the OFF state require a longer time to turn ON.
The active pull-down ECL circuit illustrated in FIG. 2 has a NOR phase output and operates as follows. A pulse (having the waveform obtained by electrically differentiating an inverted phase signal of the signal applied to the base of emitter follower transistor Q16 with capacitor C11 and resistor R14) is applied to the base of pull-down transistor Q17 from the collector of the transistor Q12 of the inverted phase side of the current switch circuit. When an input changes to the high level from the low level, the pulse is generated. The pulse is applied to the base of pull-down transistor Q17 to transitionally turn it ON to discharge the capacitive load CL. Since the emitter impedance of transistor Q17 is sufficiently low, the capacitive load CL is quickly discharged. Further, capacitor C12 is transitionally charged through the transistor Q17 by the charge discharged from the capacitive load CL. The charge of the capacitor C12 is thereafter discharged through resistor R15.
FIG. 3 is a schematic diagram of an active pull-down ECL circuit having an OR phase output which is also associated with the prior art. This circuit consists of transistors Q21-Q27, resistors R21-R25, and capacitors C21, C22. Moreover, the circuit has the same construction and operation as the circuit illustrated in FIG. 2 except that the pulse applied to pull-down transistor Q27, is from the collector of transistor Q21 of the current switch circuit, while the base of the emitter follower transistor Q26 is connected to the collector of transistor Q22 of the current switch circuit.
FIG. 4 is a schematic diagram of an active pull-down ECL circuit having OR/NOR phase outputs which is associated with the prior art. This circuit consists of transistors Q31-Q41, resistors R31-R37, and capacitors C31-C34. The pulse applied to the base of pull-down transistor Q37 or Q41 is extracted from the inverted phase output at output terminals 35 or 34. In this case, charge is quickly discharged for high speed switching to the low level from the high level using an operation similar to that described above. However, this ECL circuit has a higher logic function capability because it allows use of the outputs in both OR/NOR phases. Thus, more complicated circuits can be equivalently formed even with the same number of gates. Thus, even in the case where an active pull-down circuit is used for further improving the operation rate of the ECL circuit, in order to increase the logic function capability of the circuit the outputs of both OR/NOR phases must be used.
FIG. 5 is a schematic diagram of an active pull-down ECL circuit having a construction similar to that of FIG. 4. This circuit consists of transistors Q51-Q61, resistors R51-R57, and capacitors C51-C54. As shown in FIG. 5, signals can be extracted from the collectors of transistors Q51, Q52 of the current switch circuit and supplied to pull-down transistors Q57, Q61. It is known that the switching rate of the current switch circuit is lowered when a capacitor C51 or C53 is connected to the collector of the transistor Q51 or Q52 of the current switch circuit. However, in the case of a single phase ECL circuit (OR or NOR), as shown in FIGS. 2 and 3, only the inverted phase signal is used for the active pull-down circuit and is not used for the base signal of emitter follower transistor. Thus, the addition of capacitor C11 or C21 to the ECL circuit will not cause the switching rate to be lowered. However, when both phases OR/NOR are used in the ECL circuit, as shown in FIG. 5, capacitor C53 and C51 are respectively connected to the collector of transistor Q51 and Q52 of the current switch circuit for extracting a signal from the base of the emitter follower transistors Q56 and Q60, respectively. Therefore, the switching rate is lowered and improvement over an ordinary ECL circuit is lost. This problem can be compensated to a limited extent by either making the value of resistor R53 smaller or raising the voltage of terminal 53 to increase the current of the current switch circuit. However, as discussed above, this increases power dissipation, thus making unsuitable for high density LSI.
Furthermore, even with the method of extracting the pulse shown in FIG. 4 from the output terminals 34 or 35 having the inverted phase, capacitors C31 and C33 are additionally connected, thereby increasing the switching time. Further, in the case where the capacitive load CL is connected to the output of the inverted phase, the output waveform is dulled and, as a result, an adequate pulse can no longer be applied to the base of pull-down transistor Q37 or Q41. In addition, since the inverted phase output signal is applied to the base of pull-down transistor Q37 or Q41 is obtained from the input terminal 31 through two stages of transistors Q32 and Q36 or Q31 and Q40, the inverted phase output takes a longer time to reach pull-down transistor Q37 or Q41 which causes the time discharge of capacitive load CL to be delayed.
Therefore, with any of the prior art methods, it is very difficult to simultaneously use a high speed active pull-down ECL circuit with the OR/NOR phases. Further, high speed operation can be maintained only by forming the ECL circuit with OR/NOR phases with individual gates and by increasing the current through the current switch circuit. However, this causes the power dissipation to become large which prevents an increase in the integration density of the LSI. As a result, these prior art methods are not suitable for use with LSI of high integration density, particularly when the capacitive load is large. Therefore, a circuit which ensures high speed switching to a low level from a high level and simultaneously uses both OR and NOR phases in a high speed LSI circuit with an active pull-down structure has long been required.